1. Technical Field
The present invention relates to an amplifier circuit for high-speed operation, which is protected from excess current.
Recently, there has been increasing demand for a high-speed large-scale integrated circuit which is capable of handling a large current for driving a peripheral circuit. Demand exists for an analog LSI as well as a digital LSI. It is necessary to speed up the operation of an analogue circuit and to drive it with a large current. Thus, an amplifier such as an operation amplifier must be speeded up or subjected to a large current drive. It is necessary to drive the analog circuit with a large current. Thus, the LSI itself and the peripheral circuit must be protected from an excess current upon an excess load such as a load short-circuit by a current-limiting function provided to the LSI itself or to the peripheral circuit.
2. Related Art
FIG. 1 shows an example of a differential amplifier circuit (such as a comparator) composed of a CMOS. T.sub.1 and T.sub.2 are a pair of differential N-channel driving transistors and T.sub.3 and T.sub.4 form a current mirror circuit by using a P-channel load transistor. T.sub.5 is a P-channel transistor in the output stage and I.sub.1 and I.sub.2 are constant current sources. +IN and -IN, respectively, are the non-inverting and inverting inputs, and OUT is the output.
In this differential amplifier circuit, T.sub.1 turns on and T.sub.2 turns off when -IN&gt;+IN. Thus, the voltage level of node N.sub.3 then increases, thereby turning T.sub.5 off and providing the output OUT with L level. Conversely, T.sub.1 turns off and T.sub.2 turns on when -IN&lt;+IN. Thus, the voltage level of node N.sub.3 decreases, thereby turning T.sub.5 on and providing output OUT with H level. When the transistor operates in saturation region, the above recited ON state means that a current larger than the standard operating point current is caused to flow and the OFF state means that a current smaller than the standard operating point current is caused to flow.
As shown in FIG. 2A, when an excess difference input voltage V.sub.(-IN) -V.sub.(+IN) is applied to this circuit, T.sub.1 turns on and T.sub.2 turns off, thereby enabling transistor T.sub.1 to cause a whole output current of a constant current source I.sub.1 to flow and enabling transistor T.sub.2 to cause a current I.sub.T2 to be 0. The current of transistor T.sub.1 is equal to that of transistor T.sub.3, and T.sub.3 and T.sub.4 form a current mirror circuit. Thus, the current of T.sub.4 is proportional to the current of T.sub.3 (the current of T.sub.4 is the same as the that of T.sub.3.) Accordingly, the current I.sub.T4 of transistor T.sub.4 tends to increase as shown in FIG. 2C, but the current I.sub.T4 can not flow as transistor T.sub.2 is turned off. Transistor T.sub.4 is strongly driven and the voltage drop between the drain and source becomes almost 0. Thus, the potential V.sub.N3 of node N.sub.3 increases to the source voltage V.sub.DD. Thus, transistor T.sub.5 turns off and the output voltage V.sub.OUT becomes equal to the voltage V.sub.SS (which is 0 Volts in this embodiment).
If the excess difference input ends instantaneously as shown in FIG. 2A, and thereafter the input difference becomes 0, transistors T.sub.1 and T.sub.2 turn on and cause I.sub.1 /2 to flow. This I.sub.1 /2 is equal to the current caused to flow by transistors T.sub.3 and T.sub.4. Node N.sub.3 is driven at the voltage V.sub.DD by the excess difference input. When the difference input is 0, the voltage decreases more. However, when I.sub.T4 is equal to I.sub.T2, it takes time for node N.sub.3 to discharge the charge therein. Thus, the potential N.sub.3 of node N.sub.3 gradually decreases, as shown in FIG. 2D. When the voltage V.sub.N3 is less than V.sub.DD -V.sub.th (where V.sub.th is the threshold voltage of transistor T.sub.5), transistor T.sub.5 turns on, thereby causing the current I.sub.T5 to flow and voltage V.sub.OUT to increase.
As stated above, if an excess input is applied to the amplifier, the internal voltage of the amplifier deviates from its normal operation and takes time to be restored. Thus, it can not perform a normal operation within a restoring period, and high-speed operation is not achieved.
To solve this problem, the prior art is provided with the countermeasure shown in FIG. 3. In FIG. 3A, diodes D.sub.1 and D.sub.2 of reverse parallel connection are connected between nodes N.sub.2 and N.sub.3, thus limiting the amplitude of the potential of node N.sub.3 and tending to produce high-speed operation. The limitation of the amplitude when the potential of node N.sub.3 tends to increase to the voltage V.sub.DD, can only be performed by diode D.sub.1. In FIG. 3B, the current sources I.sub.3 and I.sub.4 are inserted between the nodes N.sub.2 to N.sub.3 and the low potential side source V.sub.SS to prevent transistors T.sub.3 and T.sub.4 from being in a non-current state when transistors T.sub.1 or T.sub.2 are cut off by the excess input and to prevent the potential increase in nodes N.sub.2 and N.sub.3 from being excessive. In FIG. 3C, transistors T.sub.6 and T.sub.7 are connected between the nodes N.sub.2 and N.sub.3 and node N.sub.1, and transistors T.sub.6 and T.sub.7 are controlled by -IN and +IN so that T.sub.7 is on when T.sub.1 is off and T.sub.6 is on when T.sub.2 is off, thereby preventing transistors T.sub.3 and T.sub.4 from being in a non-current state and preventing an excess potential increase in nodes N.sub.2 and N.sub.3. The same parts are represented by the same symbols throughout the all drawings.
However, in the circuit shown in FIG. 3A, the CMOS IC should be formed of a MOS diode. When the CMOS IC is formed of junction type diodes D.sub.1 and D.sub.2, a parasitic thyristor is formed, causing latch up phenomena. The circuits shown in FIGS. 3B and 3C do not perform an amplitude limitation directly. Thus, they can not achieve a sufficient effect and can not perform a sufficient high speed operation.
Next, the excess current is discussed. If a load short-circuit occurs, an excess output current flows and the transistor in the output stage is destroyed. In a small-current FET, a load short-circuit does not cause a great problem as the load current is suppressed because of the saturation characteristic of a small current FET, but a circuit having a large current-driving capability has the problem of a load short-circuit.
FIG. 4 shows an example of a circuit in which an excess current is prevented by using an emitter-follower. Q.sub.1 to Q.sub.6 are bipolar transistors forming a differential pair at the input stage. The non-inverting and inverting inputs +IN and -IN are applied to the bases of transistors Q.sub.4 and Q.sub.3. Transistors Q.sub.5 and Q.sub.6 form a current mirror. I.sub.5 -I.sub.8 form a constant current source, bipolar transistors Q.sub.10 -Q.sub.12 form an output stage, Q.sub.7 -Q.sub.9 form the driving stage, C.sub.1 is a phase compensation capacitor, R.sub.1 is a current sensing resistor, D.sub.5 -D.sub.7 are level shifting diodes, and Q.sub.13 is a bipolar transistor. Resistor R.sub.1 and transistor Q.sub.13 prevent an excess current.
When the load current increases and hence the voltage drop across the resistor R.sub.1 increases, transistor Q.sub.13 is be turned on, and the base current of the Darlington pair Q.sub.10 and Q.sub.11 is bypassed. As a result, transistors Q.sub.10 and Q.sub.11 are driven in the direction such that they are turned off and the load current is prevented from becoming excessive. More specifically, when an external load is supplied at a current I from the output terminal OUT, the current I is mainly supplied through Q.sub.11 and R.sub.1. When the current I increases and hence the voltage drop IR.sub.1 across the resistor R.sub.1 exceeds V.sub.BEO (the specific base-to-emitter voltage of approximately 0.6-0.7 volts) of the transistor Q.sub.13, the transistor Q.sub.13 will begin to conduct. Then, the base voltage of Q.sub.10 and hence the base voltage of Q.sub.11 will be decreased and the emitter voltage of Q.sub.11 and the output voltage at OUT will be subsequently decreased, thereby reducing the supply current I to the external load. Finally, the current I will be limited to a level which satisfies IR.sub.1 .apprxeq.0.6-0.7 volts (in other words, to the extent that Q.sub.13 begins to conduct a current).
The circuit of FIG. 4, which performs a current limiting function, is a bipolar transistor circuit, not a CMOS circuit. With a CMOS amplifier, a source follower does not have as low an impedance as an emitter follower of a bipolar amplifier. Thus, a CMOS circuit corresponding the circuit of FIG. 4 is not used. In a CMOS configuration, the currents of transistor T.sub.5 and current source I.sub.2 are made high in FIG. 1, thereby providing high-current driving capability.
With the system of FIG. 3A adapted to speed up the operation of the CMOS amplifier, there are problems with the protection diodes D.sub.1 and D.sub.2. With the systems of FIGS. 3B and 3C, on the other hand, a sufficient effect cannot be expected. There is a bipolar transistor amplifier sufficient for overcurrent limiting, as shown in FIG. 4, but there is no satisfactory CMOS amplifier.